1. Field of the Invention
The present invention relates to testing for high-speed point-to-point link networks. More particularly, the invention relates to how loop back testing may be applied for testing an interconnect architecture utilizing point-to-point links. For example, the following application details a loop back entry and exit scheme that may be used in connection with the other related patent application.
2. Description of the Related Art
As the technology for manufacturing integrated circuits advances, more logic functions are included in a single integrated circuit device or a system on a chip (SoC). Modem integrated circuit (IC) devices include large numbers of gates on a single semiconductor chip, with these gates interconnected so as to perform multiple and complex functions. The fabrication of an IC incorporating such Very Large Scale Integration (VLSI) must be error free, as any manufacturing defect may prevent the IC from performing all of the functions that an IC or SoC is designed to perform. Such demands require verification of the design of the IC or SoC and also various types of electrical testing after the IC or SoC is manufactured.
However, as the complexity of the ICs and SoCs increase, so does the cost and complexity of verifying and electrically testing the individual IC or multiple ICs in a system. Testing, manufacturing costs and design complexity increase dramatically because of the increasing number of functional pins on the integrated devices and SoC. With the increased number of I/O pins on each integrated device or system, the complexity and cost of testing each I/O pin has increased. Furthermore, the complexity of testing has increased with the advent of computer architectures utilizing multiple agents, such as, a plurality of caching agents and home agents coupled to a network fabric. For example, a scheme with a master and slave agent may require either of the following that increase testing complexity or utilize additional hardware resources: an external control for chip set agents, lack of standardization of testing high speed I/O interfaces, and testing registers for both master and slave agents.